High-Speed Ternary Half adder based on GNRFET

Document Type: Original Research Paper

Authors

1 Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran

2 Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran

10.22034/jna.2019.668030

Abstract

Superior electronic properties of graphene make it a substitute candidate for beyond-CMOS
nanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, and
quantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,
are used to design the digital circuits. This paper presents a new design of ternary half adder based
on graphene nanoribbon FETs (GNRFETs). Due to reducing chip the area and integrated circuit (IC)
interconnects, ternary value logic is a good alternative to binary logic. Extensive simulations have been
performed in Hspice with 15-nm GNRFET technology to investigate the power consumption and delay.
Results show that the proposed design is very high-speed in comparison with carbon nanotube FETs
(CNTFETs). The proposed ternary half adder based on GNRFET at 0.9V exhibiting a low power-delayproduct
(PDP) of ~10-20 J, which is a high improvement in comparison with the ternary circuits based
on CNTFET, lately proposed in the literature. This proposed ternary half adder can be advantageous in
complex arithmetic circuits.

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