Document Type: Original Research Paper
Department of Electrical Engineering, Guilan University, Rasht, Iran.
Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran
In this paper, we propose an innovative and low computational cost approach that can be used to find optimal values of parameters of a nanoscale dual gate tunneling field-effect transistor (DG-TFET). In this way, after obtaining analytical expressions for potential and energy bands of the device using the Poisson equation, the tunneling length is extracted at source-channel and channel-drain tunnel junctions in the AMBIPOLAR, Off and On states. Due to the tunneling length equation, the different values of gate work function and dielectric constant of the device are swept to determine the minimum and maximum design limits. According to the above range, the necessary checks are made to reach the local optimal behaviors. These optimum points are explained based on the achievement of optimal device performance. The accuracy and consistency of the proposed model is validated with the TCAD simulation results. The present model can be a handful for the study of TFET performance.